The CD-SEM is often used for inline process control. Measurements are extracted from top-down images based on secondary electron collection while scanning the specimen. However, with regular CD-SEM imaging, material dependent differentiation and quantification is not possible, as grey level variation on an area of interest, e.g., a pad area, is limited.
Further, known approaches for inline monitoring often involve optical techniques such as reflectometry, for example. However, to execute such measurements, a dedicated test pattern size of approximately 70 micrometers (μm)×70 μm, for example, needs to be placed in a sacrificial area of the chip, e.g., spot size of measurement system is 30 μm to 50 μm. These test structures are generally non-electrical patterns. As a result, correlation to electrical parameters is difficult. In addition, due to the topographical effects and density variations across a chip, the measurement does not always represent what happened in the chip and to the pads/vias with much smaller areas. Currently, the wafer has to be brought to an analytical lab for cross sectioning and verified with destructive physical analysis, e.g., transmission electron microscopy (TEM) or cross-section scanning electron microscope (X-SEM) imaging. Consequently, the wafer is lost and the turnaround time is quite high, e.g., in the range of a week, and several thousands of wafers can be at risk as a result.
Therefore, for process monitoring and device reliability insurance for thin layers or thin films it is important to have feedback information as to whether via pads in upper back-end-of-line (BEOL) layers are opened, partially opened, or closed post etching. However, due to the particularly small size of the via pads, e.g., 9 μm2 to 1600 μm2, alternate measurement approaches using energy dispersive x-ray (EDX) may not yield required sensitivity as high voltages of 5 kilovolts (kV) and up are required. Moreover, thin residual layers of a few nanometers, e.g., 1 nm to 10 nm, are not easy to dissolve as the penetration depth for electrons is too high, and the main EDX signal comes from the lower layer. Further, optical film measurements also may not be an option since the pads are often too small, e.g., a minimum of 2500 μm2 is generally required for optical approaches.
In addition, during typical via etch steps (excluding trench first via last (TVFL)), the etch stops in tetraethyl orthosilicate (TEOS) and/or BLOK layers. However, sometimes the etching depth target is not optimally reached so that excess residual TEOS and/or BLOK remains. As a result, at the final etch step, the via remains unopened, and at the fill step, contact cannot be made. Consequently, a number of wafers in progress (WIP) may be affected until the issue has been detected. Ideally, at a via-etch CD measurement step, an inspection of residual layer thickness would be desired to estimate the successful via etch process down to target depth. Moreover, depth measurement by atomic force microscopy (AFM) is not possible due to the dimensions of the vias.
A need therefore exists for methodology enabling inline determination of an amount of residual material on a via pad and a thickness of a residual layer in a via after via etch.